/**
 @file sys_at_datapath.h

 @date 2020-09-01

 @version v2.0

 The file contains chip independent related APIs of sys layer
*/

#ifndef _SYS_AT_DATAPATH_H
#define _SYS_AT_DATAPATH_H
#ifdef __cplusplus
extern "C" {
#endif


/* Start DMPS Add */
#define SYS_AT_CORE_NUM               2
#define SYS_AT_TXQM_NUM_PER_DP        2
#define SYS_AT_NW_MAC_CLIENT_PER_DP   32
#define SYS_AT_MAX_MAC_CLIENT_PER_DP  33   /* with CPUMAC */
#define SYS_AT_CHAN_NUM_PER_DP        26
#define SYS_AT_CHAN_NUM_PER_PP        52
#define SYS_AT_NW_CHAN_NUM_PER_DP     24
#define SYS_AT_NW_CHAN_NUM_PER_PP     48
#define SYS_AT_DP_NUM_PER_PP          2
#define SYS_AT_MAX_CHAN_NUM           512
#define SYS_AT_MAC_CLIENT_PER_TXQM    16
#define SYS_AT_CHAN_NUM_PER_TXQM      16

#define SYS_AT_MISC_CHAN_ID_IN_DP    24
#define SYS_AT_LOOP_CHAN_ID_IN_DP    25
#define SYS_AT_MISC_MAC_CLIENT_IN_DP 32
#define SYS_AT_LOOP_MAC_CLIENT_IN_DP 33

#define AT_CPUMAC  /*BR_TODO*/

#define SYS_AT_MAX_CAL_LEN 512

#define SYS_SCALE_FACTOR    1000

#define SYS_AT_DP_BW_MAX    1700
#define SYS_AT_CLK_DEFAULT  1350
#define SYS_AT_MAX_BANDWIDTH_PER_TXQM 800  /*800G*/
#define SYS_AT_MAX_BANDWIDTH_PER_MCMAC 800
#define SYS_AT_MAX_MAC_CAL_ENTRY 160

#define SYS_AT_CPUMAC_SERDES_NUM 4
#define SYS_AT_MAX_NETWORK_PORT_NUM 160
#define SYS_AT_NW_SERDES_NUM_PER_CORE 160
#define SYS_AT_NW_SERDES_NUM SYS_AT_NW_SERDES_NUM_PER_CORE*SYS_AT_CORE_NUM
#define AT_DP_NUM_PER_CORE 8
#define AT_DP_NUM_PER_PP 2
#define AT_PP_NUM_PER_CORE 4
#define AT_MCMAC_NUM_PER_DP 3
#define AT_MAC_ID_NUM_PER_MCMAC 8
#define AT_CPUMAC_PER_CORE 2
#define AT_MAX_XPIPE_CHAN 3

#define AT_MCMAC_NUM_PER_CORE 20
#define AT_MCU_NUM_PER_CORE   21

#define AT_MAC_400_NUM_PER_MCMAC 2
#define AT_SERDES_NUM_PER_MCMAC 8
#define AT_SERDES_NUM_PER_HSS  4
#define AT_HSS_NUM_PER_MCMAC   2
#define AT_LPORT_NUM_PER_MCMAC 8
#define AT_ENTRY_NUM_PER_MCMAC 8
#define AT_PCS_NUM_PER_MCMAC 8
#define AT_SERDES_NUM_MAX  324
#define AT_SERDES_CPUMAC_START_ID_CORE0  320
#define AT_SERDES_CPUMAC_START_ID_CORE1  322
#define AT_SERDES_CPUMAC_DPHSS  40

#define AT_CHAN_NUM_PER_DP_NW 24
#define AT_CHAN_NUM_PER_CORE  208
#define AT_NW_CHAN_NUM_PER_CORE  192
#define AT_MAX_NW_CHAN_PER_CORE  194 /* 192 network ports and 2 cpumac ports */
#define AT_LPORT_NUM_PER_DP 24
#define AT_LPORT_NUM_PER_CORE 192
#define AT_LPORT_NUM_PER_PP 48

#define AT_MAX_NETWORK_PORT_NUM_PER_CORE 192

#define AT_SERDES_NUM_PER_CORE 160
#define AT_MAC_NUM_PER_CORE 160
#define AT_PCS_NUM_PER_CORE 160
#define AT_FEC_NUM_PER_CORE 160

#define SYS_AT_MAC_GROUP_NUM_HALF_CORE 10
#define SYS_AT_HSS_NUM_PER_CORE (AT_MCMAC_NUM_PER_CORE*AT_HSS_NUM_PER_MCMAC)

#define SYS_AT_SERDES_PG_FIRST 8
#define SYS_AT_SERDES_PG_LAST  151
#define SYS_AT_112G_SERDES_FIRST 16
#define SYS_AT_112G_SERDES_LAST  143
#define SYS_AT_SUPPORT_112G_FIRST 48
#define SYS_AT_SUPPORT_112G_LAST  111
#define SYS_SPECIAL_RSV_PORT_START 252
#define SYS_SPECIAL_RSV_PORT_NUM 4

#define AT_CPUMAC_SERDES_SUPPORT_SPEED ((1 << SERDES_SPEED_0G) | (1 << SERDES_SPEED_1_25G) | (1 << SERDES_SPEED_3_125G)\
                                        | (1 << SERDES_SPEED_10_3125G) | (1 << SERDES_SPEED_11_40625G) | (1 << SERDES_SPEED_12_5G)\
                                        | (1 << SERDES_SPEED_12_96875G) | (1 << SERDES_SPEED_10_9375G) | (1 << SERDES_SPEED_25_78125G)\
                                        | (1 << SERDES_SPEED_28_125G) | (1 << SERDES_SPEED_26_5625G) | (1 << SERDES_SPEED_27_34375G)\
                                        | (1 << SERDES_SPEED_27_78125G))
#define AT_56G_SERDES_SUPPORT_SPEED    ((1 << SERDES_SPEED_0G)\
                                        | (1 << SERDES_SPEED_10_3125G) | (1 << SERDES_SPEED_11_40625G) | (1 << SERDES_SPEED_12_5G)\
                                        | (1 << SERDES_SPEED_12_96875G) | (1 << SERDES_SPEED_10_9375G) | (1 << SERDES_SPEED_25_78125G)\
                                        | (1 << SERDES_SPEED_28_125G) | (1 << SERDES_SPEED_26_5625G) | (1 << SERDES_SPEED_27_34375G)\
                                        | (1 << SERDES_SPEED_27_78125G) | (1 << SERDES_SPEED_20_625G) | (1 << SERDES_SPEED_51_5625G)\
                                        | (1 << SERDES_SPEED_53_125G) | (1 << SERDES_SPEED_56_25G))
#define AT_112G_SERDES_SUPPORT_SPEED_LOW  (AT_56G_SERDES_SUPPORT_SPEED | (1 << SERDES_SPEED_42_5G))
#define AT_112G_SERDES_SUPPORT_SPEED_HIGH (AT_112G_SERDES_SUPPORT_SPEED_LOW | (1 << SERDES_SPEED_103_125G)\
                                            | (1 << SERDES_SPEED_106_25G) | (1 << SERDES_SPEED_112_5G))

#define SYS_AT_USELESS_ID8   0xff
#define SYS_AT_USELESS_ID16  0xffff
#define SYS_AT_USELESS_ID32  0xffffffff
                                        
                                        
#define AT_MAX_QMGR_CREDIT_PER_DP      640
#define AT_MAX_BR_SOP_CREDIT_PER_DP    1536
#define AT_MAX_BR_BODY_CREDIT_PER_DP   512
#define AT_MAX_BR_LOCAL_CREDIT_PER_DP  320
#define AT_MAX_BR_REMOTE_CREDIT_PER_DP 512
#define AT_MAX_EPE_CREDIT_PER_TXQM     320
#define AT_MAX_NETTX_CREDIT_PER_TXQM   320

#define AT_NETTX_CAL_ENTRY_PRT_TXQM    160
#define AT_NETTX_CAL_ENTRY_PRT_TXQM_LOW_CLK 80
#define AT_NETTX_CAL_INVAILD_VALUE     127

#define SYS_AT_BMP_IS_SET(value, bmp_mask)             ((bmp_mask) == ((value) & (bmp_mask)))
#define SYS_AT_GET_PORT_IDX(dport)                     (dport % SYS_AT_CPUMAC_SERDES_NUM)
#define SYS_AT_MAP_SERDES_TO_HSS_IDX(serdes_id)        ((serdes_id) / AT_SERDES_NUM_PER_HSS)
#define SYS_AT_MAP_SERDES_TO_CORE_HSS(serdes_id)        ((serdes_id) < AT_SERDES_CPUMAC_START_ID_CORE0 ? \
                                                         (((serdes_id) % AT_SERDES_NUM_PER_CORE) / AT_SERDES_NUM_PER_HSS) : \
                                                         AT_SERDES_CPUMAC_DPHSS)
#define SYS_AT_MAP_SERDES_TO_LANE_ID(serdes_id)        ((serdes_id) % AT_SERDES_NUM_PER_HSS)
#define SYS_AT_GET_MAC_GROUP_BY_LSD_SC(lsd)            (lsd / AT_SERDES_NUM_PER_MCMAC)
#define SYS_AT_GET_MAC_GROUP_BY_LSD_DC(lsd)            ((lsd / AT_SERDES_NUM_PER_MCMAC) % AT_MCMAC_NUM_PER_CORE)

#define SYS_AT_IS_MISC_PORT(port_type) ((SYS_DMPS_OAM_PORT == port_type) || (SYS_DMPS_DMA_PORT == port_type)\
                                        ||(SYS_DMPS_CPU_MAC_PORT == port_type) || (SYS_DMPS_CPUMAC_NETWORK_PORT == port_type))
#define SYS_AT_IS_LOOP_PORT(port_type) ((SYS_DMPS_ILOOP_PORT == port_type) || (SYS_DMPS_ELOOP_PORT == port_type))

#define SYS_AT_IS_NW_SERDES(serdes_id) ((serdes_id < SYS_AT_CORE_NUM * SYS_AT_NW_SERDES_NUM_PER_CORE) ? TRUE : FALSE)
#define SYS_AT_GET_CORE_BY_CPU_SERDES(serdes_id) ((serdes_id < DMPS_MAX_MAC_NUM_PER_CORE * DMPS_MAX_CORE_NUM + AT_CPUMAC_PER_CORE) ? 0 : 1)
#define SYS_AT_GET_CORE_BY_NW_SERDES(serdes_id) ((serdes_id < SYS_AT_NW_SERDES_NUM_PER_CORE) ? 0 : 1)
#define SYS_AT_GET_CORE_BY_SERDES(serdes_id) (SYS_AT_IS_NW_SERDES(serdes_id) ?  \
                                                SYS_AT_GET_CORE_BY_NW_SERDES(serdes_id) : SYS_AT_GET_CORE_BY_CPU_SERDES(serdes_id))
#define SYS_AT_IS_NW_CHAN(sub_chan) ((sub_chan < AT_CHAN_NUM_PER_DP_NW) ? TRUE : FALSE)

#define SYS_AT_SUBTYPE_1PP         DRV_CHIP_SUB_TYPE_MAX

#define SYS_AT_GET_CHIP_TYPE(p_lchip) sys_at_datapath_get_chip_type(p_lchip)
#define SYS_AT_CHIP_IS_DC(p_lchip)    sys_at_datapath_chip_is_dc(p_lchip)
#define SYS_AT_MAC_GROUP_IS_VAILD(p_lchip, p_core_id, p_mac_group_id) sys_at_datapath_mac_group_is_valid(p_lchip, p_core_id, p_mac_group_id)
#define SYS_AT_PP_IS_VAILD(p_lchip, p_core_id, p_pp_id) sys_at_datapath_pp_is_valid(p_lchip, p_core_id, p_pp_id)

#define AT_CHIP_SERDES_SCALE(p_lchip) _sys_at_datapath_serdes_scale(p_lchip)
#define AT_CHIP_IS_SERDES_AG(p_lchip)      ((SYS_DMPS_DB_SERDES_SCALE_0 == AT_CHIP_SERDES_SCALE(p_lchip))\
                                                || (SYS_DMPS_DB_SERDES_SCALE_3 == AT_CHIP_SERDES_SCALE(p_lchip)))
#define AT_CHIP_IS_SERDES_AG_HIGH(p_lchip)    (SYS_DMPS_DB_SERDES_SCALE_3 == AT_CHIP_SERDES_SCALE(p_lchip))
#define AT_CHIP_IS_SERDES_AG_LOW(p_lchip)     (SYS_DMPS_DB_SERDES_SCALE_0 == AT_CHIP_SERDES_SCALE(p_lchip))
#define AT_CHIP_IS_SERDES_PG_HIGH(p_lchip)    (SYS_DMPS_DB_SERDES_SCALE_1 == AT_CHIP_SERDES_SCALE(p_lchip))
#define AT_CHIP_IS_SERDES_PG_LOW(p_lchip)     (SYS_DMPS_DB_SERDES_SCALE_2 == AT_CHIP_SERDES_SCALE(p_lchip))
#define AT_CHIP_IS_SERDES_DCM_PG_LOW(p_lchip) (SYS_DMPS_DB_SERDES_SCALE_5 == AT_CHIP_SERDES_SCALE(p_lchip))
#define AT_SERDES_PG_LOW_MAX_SPEED_PER_MCMAC 400000000

#define SYS_AT_IS_1TO2_TXQM_AGG_GROUP(p_lchip, p_mac_group_id) \
        (((DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip)) && (AT_CHIP_IS_SERDES_AG_HIGH(p_lchip))) &&\
              (((1 == p_mac_group_id) || (9 == p_mac_group_id)\
            || (10 == p_mac_group_id) || (18 == p_mac_group_id))))

#define SYS_AT_IS_1TO2_MAC_AGG_GROUP(p_lchip, p_mac_group_id) \
        ((((AT_CHIP_IS_SERDES_AG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) &&\
               ((0 == p_mac_group_id) || (2 == p_mac_group_id)\
            || (4 == p_mac_group_id) || (5 == p_mac_group_id)\
            || (14 == p_mac_group_id) || (15 == p_mac_group_id)\
            || (17 == p_mac_group_id) || (19 == p_mac_group_id))) ||\
        (((AT_CHIP_IS_SERDES_AG_HIGH(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) &&\
               ((0 == p_mac_group_id) || (2 == p_mac_group_id)\
            || (17 == p_mac_group_id) || (19 == p_mac_group_id))) ||\
        (((DRV_CHIP_SUB_TYPE_2 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) &&\
               ((1 == p_mac_group_id) || (3 == p_mac_group_id)\
            || (4 == p_mac_group_id) || (5 == p_mac_group_id)\
            || (6 == p_mac_group_id) || (7 == p_mac_group_id)\
            || (12 == p_mac_group_id) || (13 == p_mac_group_id)\
            || (14 == p_mac_group_id) || (15 == p_mac_group_id)\
            || (16 == p_mac_group_id) || (18 == p_mac_group_id))) ||\
        (((DRV_CHIP_SUB_TYPE_4 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_DCM_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_3 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) &&\
               ((4 == p_mac_group_id) || (5 == p_mac_group_id)\
            || (6 == p_mac_group_id) || (7 == p_mac_group_id)\
            || (12 == p_mac_group_id) || (13 == p_mac_group_id)\
            || (14 == p_mac_group_id) || (15 == p_mac_group_id))))\

#define SYS_AT_IS_1TO2_GROUP(p_lchip, p_mac_group_id) ((SYS_AT_IS_1TO2_MAC_AGG_GROUP(p_lchip, p_mac_group_id))\
                                                        || (SYS_AT_IS_1TO2_TXQM_AGG_GROUP(p_lchip, p_mac_group_id)))

#define SYS_AT_GET_REMOTE_GROUP_IN_1TO2_TXQM_AGG(p_lchip, p_local_group) \
    (((DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip)) && (AT_CHIP_IS_SERDES_AG_HIGH(p_lchip))) ? \
    ((1 == p_local_group)  ? 9 :   \
     (9 == p_local_group)  ? 1 :   \
     (10 == p_local_group) ? 18 :  \
     (18 == p_local_group) ? 10 : SYS_AT_USELESS_ID8) :    \
     SYS_AT_USELESS_ID8)    \

#define SYS_AT_GET_REMOTE_GROUP_IN_1TO2_MAC_AGG(p_lchip, p_local_group) \
    (((AT_CHIP_IS_SERDES_AG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) ? \
    ((0 == p_local_group)  ? 2 :   \
     (2 == p_local_group)  ? 0 :   \
     (4 == p_local_group)  ? 5 :   \
     (5 == p_local_group)  ? 4 :   \
     (14 == p_local_group) ? 15 :   \
     (15 == p_local_group) ? 14 :   \
     (17 == p_local_group) ? 19 :  \
     (19 == p_local_group) ? 17 : SYS_AT_USELESS_ID8) :    \
    ((AT_CHIP_IS_SERDES_AG_HIGH(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) ? \
    ((0 == p_local_group)  ? 2 :   \
     (2 == p_local_group)  ? 0 :   \
     (17 == p_local_group) ? 19 :  \
     (19 == p_local_group) ? 17 : SYS_AT_USELESS_ID8) :    \
    ((DRV_CHIP_SUB_TYPE_2 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) ?  \
    ((1 == p_local_group)  ? 3 :   \
     (3 == p_local_group)  ? 1 :   \
     (4 == p_local_group)  ? 5 :   \
     (5 == p_local_group)  ? 4 :   \
     (6 == p_local_group)  ? 7 :   \
     (7 == p_local_group)  ? 6 :   \
     (12 == p_local_group) ? 13 :   \
     (13 == p_local_group) ? 12 :   \
     (14 == p_local_group) ? 15 :   \
     (15 == p_local_group) ? 14 :   \
     (16 == p_local_group) ? 18 :  \
     (18 == p_local_group) ? 16 : SYS_AT_USELESS_ID8) :    \
    ((DRV_CHIP_SUB_TYPE_4 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_DCM_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_3 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) ?  \
    ((4 == p_local_group)  ? 5 :   \
     (5 == p_local_group)  ? 4 :   \
     (6 == p_local_group)  ? 7 :   \
     (7 == p_local_group)  ? 6 :   \
     (12 == p_local_group) ? 13 :   \
     (13 == p_local_group) ? 12 :   \
     (14 == p_local_group) ? 15 :   \
     (15 == p_local_group) ? 14 : SYS_AT_USELESS_ID8) :    \
     SYS_AT_USELESS_ID8)    \

#define SYS_AT_GET_REMOTE_GROUP(p_lchip, p_local_group) \
    ((SYS_AT_USELESS_ID8 == SYS_AT_GET_REMOTE_GROUP_IN_1TO2_TXQM_AGG(p_lchip, p_local_group)) ? \
        SYS_AT_GET_REMOTE_GROUP_IN_1TO2_MAC_AGG(p_lchip, p_local_group) :   \
        SYS_AT_GET_REMOTE_GROUP_IN_1TO2_TXQM_AGG(p_lchip, p_local_group))

#define SYS_AT_IS_1TO2_MAC_AGG_TXQM(p_lchip, p_pp_id, p_dp_id, p_txqm_id) \
        ((((AT_CHIP_IS_SERDES_AG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) &&\
               (((0 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id))\
            || ((0 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id))\
            || ((3 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id))\
            || ((3 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id)))) ||\
        (((AT_CHIP_IS_SERDES_AG_HIGH(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip))) &&\
               (((0 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id))\
            || ((1 == p_pp_id) && (0 == p_dp_id) && (1 == p_txqm_id))\
            || ((2 == p_pp_id) && (0 == p_dp_id) && (1 == p_txqm_id))\
            || ((3 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id)))) ||\
        (((DRV_CHIP_SUB_TYPE_2 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_1 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) &&\
               (((0 == p_pp_id) && (0 == p_dp_id) && (1 == p_txqm_id))\
            || ((0 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id))\
            || ((1 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id))\
            || ((1 == p_pp_id) && (1 == p_dp_id) && (1 == p_txqm_id))\
            || ((2 == p_pp_id) && (0 == p_dp_id) && (1 == p_txqm_id))\
            || ((2 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id)))) ||\
        (((DRV_CHIP_SUB_TYPE_4 == SYS_AT_GET_CHIP_TYPE(p_lchip)) ||\
            ((AT_CHIP_IS_SERDES_DCM_PG_LOW(p_lchip)) && (DRV_CHIP_SUB_TYPE_3 == SYS_AT_GET_CHIP_TYPE(p_lchip)))) &&\
               (((0 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id))\
            || ((1 == p_pp_id) && (0 == p_dp_id) && (0 == p_txqm_id))\
            || ((1 == p_pp_id) && (1 == p_dp_id) && (1 == p_txqm_id))\
            || ((2 == p_pp_id) && (1 == p_dp_id) && (0 == p_txqm_id)))))\

#define SYS_AT_SERDES_SPEED_APPROXIMATE(serdes_speed) (serdes_speed >= 100000000 ? 100000000 :\
                        serdes_speed >= 50000000 ? 50000000 :\
                        serdes_speed >= 40000000 ? 40000000 :\
                        serdes_speed >= 25000000 ? 25000000 :\
                        serdes_speed >= 10000000 ? 10000000 : 0)
#define SYS_AT_GET_SERDES_NUM_BY_MODE(mode, serdes_num) \
do {\
    switch(mode)\
    {\
        case CTC_CHIP_SERDES_XFI_MODE:\
        case CTC_CHIP_SERDES_XXVG_MODE:\
        case CTC_CHIP_SERDES_LG_R1_MODE:\
        case CTC_CHIP_SERDES_CG_R1_MODE:\
        case CTC_CHIP_SERDES_NONE_MODE:\
        case CTC_CHIP_SERDES_SGMII_MODE:\
        case CTC_CHIP_SERDES_2DOT5G_MODE:\
        case CTC_CHIP_SERDES_XLG_R1_MODE:\
            serdes_num = 1;\
            break;\
        case CTC_CHIP_SERDES_LG_MODE:\
        case CTC_CHIP_SERDES_XLG_R2_MODE:\
        case CTC_CHIP_SERDES_CG_R2_MODE:\
        case CTC_CHIP_SERDES_CCG_R2_MODE:\
            serdes_num = 2;\
            break;\
        case CTC_CHIP_SERDES_XLG_MODE:\
        case CTC_CHIP_SERDES_CG_MODE:\
        case CTC_CHIP_SERDES_CCG_R4_MODE:\
        case CTC_CHIP_SERDES_CDG_R4_MODE:\
            serdes_num = 4;\
            break;\
        case CTC_CHIP_SERDES_CDG_R8_MODE:\
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:\
            serdes_num = 8;\
            break;\
        default:\
            serdes_num = 0;\
            break;\
    }\
} while(0)

#define SYS_AT_IS_112G_MODE(mode) ((CTC_CHIP_SERDES_CG_R1_MODE == (mode)) || (CTC_CHIP_SERDES_CCG_R2_MODE == (mode)) || \
                                    (CTC_CHIP_SERDES_CDG_R4_MODE == (mode)) || (CTC_CHIP_SERDES_DCCCG_R8_MODE == (mode)))

#define SYS_AT_GET_PORT_IFTYPE(mode, iftype) do {                                        \
    switch(mode)                            \
    {                                       \
        case CTC_CHIP_SERDES_SGMII_MODE:    \
            iftype = CTC_PORT_IF_SGMII;     \
            break;                          \
        case CTC_CHIP_SERDES_XFI_MODE:      \
            iftype = CTC_PORT_IF_XFI;       \
            break;                          \
        case CTC_CHIP_SERDES_2DOT5G_MODE:   \
            iftype = CTC_PORT_IF_2500X;     \
            break;                          \
        case CTC_CHIP_SERDES_XXVG_MODE:     \
        case CTC_CHIP_SERDES_LG_R1_MODE:    \
        case CTC_CHIP_SERDES_CG_R1_MODE:    \
        case CTC_CHIP_SERDES_XLG_R1_MODE:   \
            iftype = CTC_PORT_IF_CR;        \
            break;                          \
        case CTC_CHIP_SERDES_LG_MODE:       \
        case CTC_CHIP_SERDES_XLG_R2_MODE:   \
        case CTC_CHIP_SERDES_CG_R2_MODE:    \
        case CTC_CHIP_SERDES_CCG_R2_MODE:   \
            iftype = CTC_PORT_IF_CR2;       \
            break;                          \
        case CTC_CHIP_SERDES_XLG_MODE:      \
        case CTC_CHIP_SERDES_CG_MODE:       \
        case CTC_CHIP_SERDES_CCG_R4_MODE:   \
        case CTC_CHIP_SERDES_CDG_R4_MODE:   \
            iftype = CTC_PORT_IF_CR4;       \
            break;                          \
        case CTC_CHIP_SERDES_CDG_R8_MODE:   \
        case CTC_CHIP_SERDES_DCCCG_R8_MODE: \
            iftype = CTC_PORT_IF_CR8;       \
            break;                          \
        default:                            \
            iftype = CTC_PORT_IF_MAX_TYPE;  \
            break;                          \
    }                                       \
} while(0)

#define SYS_AT_IF_MODE_TO_SPEED_VALUE(mode, value)   \
do {\
    switch (mode)   \
    {\
        case CTC_CHIP_SERDES_XFI_MODE:    \
            value = 10; \
            break;  \
        case CTC_CHIP_SERDES_XLG_MODE:    \
        case CTC_CHIP_SERDES_XLG_R1_MODE:   \
        case CTC_CHIP_SERDES_XLG_R2_MODE:   \
            value = 40; \
            break;  \
        case CTC_CHIP_SERDES_CG_MODE:    \
        case CTC_CHIP_SERDES_CG_R2_MODE:    \
        case CTC_CHIP_SERDES_CG_R1_MODE:    \
            value = 100; \
            break;  \
        case CTC_CHIP_SERDES_XXVG_MODE:    \
            value = 25; \
            break;  \
        case CTC_CHIP_SERDES_LG_MODE:    \
        case CTC_CHIP_SERDES_LG_R1_MODE:    \
            value = 50; \
            break;  \
        case CTC_CHIP_SERDES_CCG_R4_MODE:    \
        case CTC_CHIP_SERDES_CCG_R2_MODE:    \
            value = 200; \
            break;  \
        case CTC_CHIP_SERDES_CDG_R8_MODE:    \
        case CTC_CHIP_SERDES_CDG_R4_MODE:    \
            value = 400; \
            break;  \
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:    \
            value = 800; \
        default:\
            value = 0;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_SPEED_VALUE(mode, value)   \
do {\
    switch (mode)   \
    {\
        case SYS_PORT_SPEED_1G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_2G5:    \
            value = 2; \
            break;  \
        case SYS_PORT_SPEED_10G:    \
            value = 10; \
            break;  \
        case SYS_PORT_SPEED_20G:    \
            value = 20; \
            break;  \
        case SYS_PORT_SPEED_25G:    \
            value = 25; \
            break;  \
        case SYS_PORT_SPEED_40G:    \
            value = 40; \
            break;  \
        case SYS_PORT_SPEED_50G:    \
            value = 50; \
            break;  \
        case SYS_PORT_SPEED_100G:    \
            value = 100; \
            break;  \
        case SYS_PORT_SPEED_200G:    \
            value = 200; \
            break;  \
        case SYS_PORT_SPEED_300G:    \
            value = 300; \
            break;  \
        case SYS_PORT_SPEED_400G:    \
            value = 400; \
            break;  \
        case SYS_PORT_SPEED_800G:    \
            value = 800; \
            break;  \
        default:\
            value = 0;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_PAUSE_TIMER_DEC_VALUE(mode, value)   \
do {\
    switch (mode)   \
    {\
        case CTC_PORT_SPEED_1G:    \
            value = 2; \
            break;  \
        case CTC_PORT_SPEED_2G5:    \
            value = 5; \
            break;  \
        case CTC_PORT_SPEED_10G:    \
            value = 20; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 50; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 20; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 25; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 50; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 50; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 100; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 100; \
            break;  \
        default:\
            value = 0;\
            break;\
    }\
} while(0)


#define SYS_AT_SPEED_MODE_TO_SPEED_MODE(mode, value)   \
do {\
    switch (mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 5; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 6; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 8; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 9; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value =10; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 11; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 12; \
            break;  \
        default:\
            value = 0;\
            break;\
    }\
} while(0)

#define SYS_AT_NETTX_SPEED_TO_CREDIT(speed, credit) \
{\
    credit =    \
        (speed>=400) ? 50 : \
        (speed>=200) ? 50 : \
        (speed>=100) ? 25 : \
        (speed>=40)  ? 12 : \
        (speed>=20)  ? 10 : \
        (speed>=15)  ? 8 :  \
        (speed>=10)  ? 5 :  \
        (speed>=5)   ? 5 :  \
        (speed>=1)   ? 3 : 0;   \
}

#define SYS_AT_SPEED_TO_BS_MODE(speed, value) \
{\
    value =    \
        (speed>=800) ? 0 : \
        (speed>=400) ? 3 : \
        (speed>=200) ? 2 : 2;   \
}


#define SYS_AT_SPEED_MODE_TO_NETTX_TIMER_THRD(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x0000008c; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x0000008c; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x00000081; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x00000040; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x00000040; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x00000020; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x0000000e; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x00000050; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x00000050; \
            break;  \
        default:\
            value = 0;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETTX_THRD(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x00030005; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x00030005; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x00020005; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x00020005; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x00030005; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x00030007; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x00030007; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x00030014; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x00030014; \
            break;  \
        default:\
            value = 0x00030005;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETTX_WALKER_END(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 7; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 3; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0; \
            break;  \
        default:\
            value = 7;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETTX_READY(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 1; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 1; \
            break;  \
        default:\
            value = 1;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETRX_BUF_LOW_THRD(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x142; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x13a; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x132; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x136; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x13a; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x142; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x142; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x142; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x142; \
            break;  \
        default:\
            value = 0x13a;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETRX_BUF_HIGH_THRD(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x192; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x18a; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x182; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x186; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x18a; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x192; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x192; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x192; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x192; \
            break;  \
        default:\
            value = 0x18a;\
            break;\
    }\
} while(0)

#define SYS_AT_SPEED_MODE_TO_NETRX_WRR_WEI(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x1; \
            break;  \
        default:\
            value = 0x1;\
            break;\
    }\
} while(0)


#define SYS_AT_SPEED_MODE_TO_NETRX_DS_CHAN_MODE(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x003d8000; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x003d8000; \
            break;  \
        default:\
            value = 0x003d8000;\
            break;\
    }\
} while(0)


#define SYS_AT_SPEED_MODE_TO_NETRX_BUF_ADMISS_CTL(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x00000028; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x00000027; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x00000026; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x0000009a; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x00000027; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x00000028; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x00000050; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x000000a0; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x00000140; \
            break;  \
        default:\
            value = 0x00000027;\
            break;\
    }\
} while(0)


#define SYS_AT_SPEED_MODE_TO_NETRX_PORT_WEI_CFG(speed_mode, value)   \
do {\
    switch (speed_mode)   \
    {\
        case CTC_PORT_SPEED_10G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_20G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_25G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_40G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_50G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_100G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_200G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_400G:    \
            value = 0x1; \
            break;  \
        case CTC_PORT_SPEED_800G:    \
            value = 0x1; \
            break;  \
        default:\
            value = 0x1;\
            break;\
    }\
} while(0)

enum sys_at_datapath_allocate_type_e
{
    SYS_AT_ALLOC_NONE_MODE,
    SYS_AT_ALLOC_NORMAL,
    SYS_AT_ALLOC_XPIPE_PMAC,
    SYS_AT_ALLOC_TYPE_BUTT
};
typedef enum sys_at_datapath_allocate_type_e sys_at_datapath_allocate_type_t;

struct sys_at_cal_info_collect_s
{
    uint8  ock;
    uint8  cl_type;     //sys_datapath_allocate_type_t
    uint16 chan_id;
    uint16 dport;
    uint32 speed;
};
typedef struct sys_at_cal_info_collect_s sys_at_cal_info_collect_t;

struct sys_at_nettx_cal_heap_s
{
    uint32 portid_order[SYS_AT_MAC_CLIENT_PER_TXQM];/*interval,per port*/
    uint32 num[SYS_AT_MAC_CLIENT_PER_TXQM];/*select num ,per port*/
    uint32 first_cal_record[SYS_AT_MAC_CLIENT_PER_TXQM];/*record the index first select*/
    uint32 cnt_history[SYS_AT_MAC_CLIENT_PER_TXQM];
    uint32 expect_margine[SYS_AT_MAC_CLIENT_PER_TXQM+1];
};
typedef struct sys_at_nettx_cal_heap_s sys_at_nettx_cal_heap_t;

enum sys_at_dmps_misc_info_item_e
{
    AT_MISC_CHAN_CPU_MAC_0 = 0,
    AT_MISC_CHAN_CPU_MAC_1,
    AT_MISC_CHAN_LOO_0,
    AT_MISC_CHAN_LOO_1,
    AT_MISC_CHAN_LOO_2,
    AT_MISC_CHAN_LOO_3,
    AT_MISC_CHAN_OAM,
    AT_MISC_CHAN_DMA_0,
    AT_MISC_CHAN_DMA_1,
    AT_MISC_CHAN_DMA_2,
    AT_MISC_CHAN_DMA_3,
    AT_MISC_CHAN_ITEM_BUTT,
};
typedef enum sys_at_dmps_misc_info_item_e sys_at_dmps_misc_info_item_t;

enum sys_at_level_e
{
    AT_CORE_LEVEL,
    AT_PP_LEVEL,
    AT_DP_LEVEL,
    AT_TXQM_LEVEL,
    AT_MAX_LEVEL,
};
typedef enum sys_at_level_e sys_at_level_t;

#define SYS_AT_GET_CORE_ID_BY_SERDES(serdes_id)     (SYS_AT_IS_CPUMAC_SERDES(serdes_id)) ? (SYS_AT_GET_CORE_ID_BY_SERDES_CPUMAC(serdes_id))\
                                                                : (SYS_AT_GET_CORE_ID_BY_SERDES_NW(serdes_id))
#define SYS_AT_GET_CORE_ID_BY_SERDES_NW(serdes_id)      ((serdes_id) / AT_SERDES_NUM_PER_CORE)
#define SYS_AT_GET_CORE_ID_BY_SERDES_CPUMAC(serdes_id)  (((serdes_id) - SYS_AT_NW_SERDES_NUM) / AT_CPUMAC_PER_CORE)
            
#define SYS_AT_GET_SERDES_PER_CORE(serdes_id)   ((serdes_id) % AT_SERDES_NUM_PER_CORE)
#define SYS_AT_GET_GROUP_ID_BY_MAC(mac_id)      ((mac_id) / AT_MAC_ID_NUM_PER_MCMAC)
#define SYS_AT_GET_MAC_IDX(mac_id)              ((mac_id) % AT_MAC_ID_NUM_PER_MCMAC)

#define  SYS_AT_MAX_MAC_NUM 320
#define SYS_AT_GET_LOGIC_SERDES_DC(core_id, logic_serdes_sc) ((core_id) * DMPS_MAX_MAC_NUM_PER_CORE + (logic_serdes_sc))
#define SYS_AT_GET_LOGIC_SERDES_SC(logic_serdes_dc) ((logic_serdes_dc) % DMPS_MAX_MAC_NUM_PER_CORE)
#define SYS_AT_GET_CORE_ID_BY_LOGIC_SERDES(logic_serdes) (SYS_AT_IS_CPUMAC_SERDES(logic_serdes) ?   \
            (((logic_serdes) - SYS_AT_NW_SERDES_NUM) / AT_CPUMAC_PER_CORE) : ((logic_serdes) / DMPS_MAX_MAC_NUM_PER_CORE))
#define SYS_AT_GET_MACID_BY_LOGIC_SERDES(logic_serdes_dc) (logic_serdes_dc)
#define SYS_AT_GET_LOGIC_SERDES_BY_MACID(mac_id) (mac_id)
#define SYS_AT_GET_MAC_IDX_BY_ID(mac_id) ((mac_id) % AT_MAC_ID_NUM_PER_MCMAC)
#define SYS_AT_GET_MAC_ID_BY_IDX(mac_group_id, mac_idx) ((mac_group_id) * AT_MAC_ID_NUM_PER_MCMAC + (mac_idx))
#define SYS_AT_GET_MAC_GROUP_ID(mac_id) ((mac_id) / AT_MAC_ID_NUM_PER_MCMAC)
#define SYS_AT_GET_LANE_IN_GROUP(serdes_id) ((serdes_id) % AT_SERDES_NUM_PER_MCMAC)
#define SYS_AT_IS_CPUMAC_SERDES(serdes_id) ((serdes_id) < SYS_AT_NW_SERDES_NUM ? FALSE : TRUE)
#define SYS_AT_GET_CHAN_ID_BY_CORE(core_id, chan_per_core) ((chan_per_core < AT_NW_CHAN_NUM_PER_CORE) ? \
            ((core_id)*AT_NW_CHAN_NUM_PER_CORE + (chan_per_core)) :\
            (SYS_AT_CHAN_CPUMAC_NETWORK_START + core_id * AT_CPUMAC_PER_CORE + chan_per_core - AT_NW_CHAN_NUM_PER_CORE))
#define SYS_AT_GET_SUBCHAN_BY_CHAN(chan_id) ((chan_id) % AT_CHAN_NUM_PER_DP_NW)
#define SYS_AT_GET_PSD_SC(psd_dc) ((psd_dc < SYS_AT_NW_SERDES_NUM) ? (psd_dc % AT_SERDES_NUM_PER_CORE) :    \
            (AT_SERDES_NUM_PER_CORE + psd_dc % AT_CPUMAC_PER_CORE))
                                    
#define SYS_AT_IS_SUPPORT_NW(mode)  ((CTC_CHIP_SERDES_XFI_MODE == mode)   || (CTC_CHIP_SERDES_XLG_MODE == mode) || \
                                    (CTC_CHIP_SERDES_XXVG_MODE == mode)   || (CTC_CHIP_SERDES_LG_MODE == mode) || \
                                    (CTC_CHIP_SERDES_CG_MODE == mode)     || (CTC_CHIP_SERDES_XLG_R1_MODE == mode) || (CTC_CHIP_SERDES_XLG_R2_MODE == mode) ||\
                                    (CTC_CHIP_SERDES_LG_R1_MODE == mode)  || (CTC_CHIP_SERDES_CG_R2_MODE == mode) || \
                                    (CTC_CHIP_SERDES_CCG_R4_MODE == mode) || (CTC_CHIP_SERDES_CDG_R8_MODE == mode) || \
                                    (CTC_CHIP_SERDES_CG_R1_MODE == mode)  || (CTC_CHIP_SERDES_CCG_R2_MODE == mode) || \
                                    (CTC_CHIP_SERDES_CDG_R4_MODE == mode) || (CTC_CHIP_SERDES_DCCCG_R8_MODE == mode))

#define SYS_AT_IS_SUPPORT_CPUMAC(mode)  ((CTC_CHIP_SERDES_XFI_MODE == mode)   || (CTC_CHIP_SERDES_2DOT5G_MODE == mode) || \
                                                                            (CTC_CHIP_SERDES_XXVG_MODE == mode))
#define SYS_AT_IS_MODE_VALID_NW(mode)  (SYS_AT_IS_SUPPORT_NW(mode) || (CTC_CHIP_SERDES_NONE_MODE == mode))
                                    
#define SYS_AT_IS_MODE_VALID_CPUMAC(mode)  (SYS_AT_IS_SUPPORT_CPUMAC(mode) || (CTC_CHIP_SERDES_NONE_MODE == mode))

#define SYS_AT_IS_1PP(chip_type) (SYS_AT_SUBTYPE_1PP == chip_type)
#define SYS_AT_GET_LANE_NUM_BY_MODE(mode, lane_num) \
do {\
    switch(mode)\
    {\
        case CTC_CHIP_SERDES_XFI_MODE:\
        case CTC_CHIP_SERDES_SGMII_MODE:\
        case CTC_CHIP_SERDES_QSGMII_MODE:\
        case CTC_CHIP_SERDES_2DOT5G_MODE:\
        case CTC_CHIP_SERDES_XXVG_MODE:\
        case CTC_CHIP_SERDES_LG_R1_MODE:\
        case CTC_CHIP_SERDES_CG_R1_MODE:\
        case CTC_CHIP_SERDES_XLG_R1_MODE:\
            lane_num = 1;\
            break;\
        case CTC_CHIP_SERDES_LG_MODE:\
        case CTC_CHIP_SERDES_XLG_R2_MODE:\
        case CTC_CHIP_SERDES_CG_R2_MODE:\
        case CTC_CHIP_SERDES_CCG_R2_MODE:\
            lane_num = 2;\
            break;\
        case CTC_CHIP_SERDES_XLG_MODE:\
        case CTC_CHIP_SERDES_CG_MODE:\
        case CTC_CHIP_SERDES_CCG_R4_MODE:\
        case CTC_CHIP_SERDES_CDG_R4_MODE:\
            lane_num = 4;\
            break;\
        case CTC_CHIP_SERDES_CDG_R8_MODE:\
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:\
            lane_num = 8;\
            break;\
        default:\
            lane_num = 0;\
            break;\
    }\
} while(0)
#define SYS_AT_GET_PORT_NUM_BY_MODE(mode, port_num) \
do {\
    switch(mode)\
    {\
        case CTC_CHIP_SERDES_QSGMII_MODE:\
            port_num = 4;\
            break;\
        case CTC_CHIP_SERDES_LG_MODE:\
        case CTC_CHIP_SERDES_CG_R2_MODE:\
        case CTC_CHIP_SERDES_XLG_MODE:\
        case CTC_CHIP_SERDES_CG_MODE:\
        case CTC_CHIP_SERDES_CCG_R4_MODE:\
        case CTC_CHIP_SERDES_CDG_R8_MODE:\
        case CTC_CHIP_SERDES_XFI_MODE:\
        case CTC_CHIP_SERDES_SGMII_MODE:\
        case CTC_CHIP_SERDES_2DOT5G_MODE:\
        case CTC_CHIP_SERDES_XXVG_MODE:\
        case CTC_CHIP_SERDES_LG_R1_MODE:\
        case CTC_CHIP_SERDES_CG_R1_MODE:\
        case CTC_CHIP_SERDES_CCG_R2_MODE:\
        case CTC_CHIP_SERDES_CDG_R4_MODE:\
        case CTC_CHIP_SERDES_DCCCG_R8_MODE:\
        case CTC_CHIP_SERDES_XLG_R1_MODE:\
        case CTC_CHIP_SERDES_XLG_R2_MODE:\
            port_num = 1;\
            break;\
        default:\
            port_num = 0;\
            break;\
    }\
} while(0)
#define SYS_AT_GET_CHAN_NUM_BY_MODE SYS_AT_GET_PORT_NUM_BY_MODE

#define SYS_AT_GET_DIC_BY_CHIP_TYPE(chip_type, dic) \
do {\
    switch(chip_type)\
    {\
        case DRV_CHIP_SUB_TYPE_1:\
            if (AT_CHIP_IS_SERDES_AG_LOW(lchip))\
            {\
                dic = g_dmps_map_ag_full;\
            }\
            else if (AT_CHIP_IS_SERDES_AG_HIGH(lchip))\
            {\
                dic = g_dmps_map_ag_full_high;\
            }\
            else if (AT_CHIP_IS_SERDES_PG_LOW(lchip))\
            {\
                dic = g_dmps_map_pg;\
            }\
            else\
            {\
                dic = g_dmps_map_ag;\
            }\
            break;\
        case DRV_CHIP_SUB_TYPE_3:\
            if (AT_CHIP_IS_SERDES_DCM_PG_LOW(lchip))\
            {\
                dic = g_dmps_map_pg;\
            }\
            else\
            {\
                dic = g_dmps_map_ag;\
            }\
            break;\
        case DRV_CHIP_SUB_TYPE_2:\
        case DRV_CHIP_SUB_TYPE_4:\
            dic = g_dmps_map_pg;\
            break;\
        case SYS_AT_SUBTYPE_1PP:\
            dic = g_dmps_map_1pp;\
            break;\
        default:\
            SYS_DATAPATH_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%s(%u): invalid chip subtype!\n", __FUNCTION__, __LINE__);\
            break;\
    }\
} while(0)

/* End DMPS Add */



/*ppPort*/
enum sys_at_chan_range_e
{
    /*channel range*/
    SYS_AT_CHAN_NETWORK_START               = 0 ,
    SYS_AT_CHAN_NETWORK_END                 = 383 ,
    SYS_AT_CHAN_CPUMAC_NETWORK_START        = 384 ,
    SYS_AT_CHAN_CPUMAC_NETWORK_END          = 387 ,
    SYS_AT_CHAN_EUNIT_START                 = 466 ,
    SYS_AT_CHAN_EUNIT_END                   = 469 ,
    SYS_AT_CHAN_LOOP_START                  = 470 ,
    SYS_AT_CHAN_LOOP_END                    = 485 ,
    SYS_AT_CHAN_DMA_START                   = 486 ,
    SYS_AT_CHAN_DMA_END                     = 493 ,
    SYS_AT_CHAN_OAM_START                   = 494 ,
    SYS_AT_CHAN_OAM_END                     = 497 ,
    SYS_AT_CHAN_CPUMAC_START                = 498 ,
    SYS_AT_CHAN_CPUMAC_END                  = 501 ,
    SYS_AT_CHAN_LOG_START                   = 502 ,
    SYS_AT_CHAN_LOG_END                     = 509 ,
    SYS_AT_CHAN_DROP                        = 510,

    SYS_AT_CHAN_MAX                 = 511
};
typedef enum sys_at_chan_range_e sys_at_chan_range_t;

struct sys_at_dmps_id_dictionary_s
{
    uint8  pp_id;
    uint8  dp_id;
    uint8  txqm_id;
    uint8  sub_chan;
    uint16 mac_client;
};
typedef struct sys_at_dmps_id_dictionary_s sys_at_dmps_id_dictionary_t;

struct sys_at_dmps_map_info_s
{
    uint8  valid_flag;
    uint8  core_id;
    uint8  pp_id;
    uint8  dp_id;
    uint8  txqm_id;
    uint8  sub_chan;
    uint16 mac_id;
    uint16 pcs_id;
    uint16 mac_client;
};
typedef struct sys_at_dmps_map_info_s sys_at_dmps_map_info_t;

typedef enum sys_at_cpumac_clocktree_cfg_item_e
{
    CpuMacClockTreeCfg_cfgClockHss20Tx0Sel      ,
    CpuMacClockTreeCfg_cfgClockHssL0TxDiv2Sel   ,
    CpuMacClockTreeCfg_cfgClockHssL0TxL2Div2Sel ,
    CpuMacClockTreeCfg_cfgClockHssL0TxMultiLane ,
    CpuMacClockTreeCfg_cfgCwgph1HssL0TxDiv      ,
    CpuMacClockTreeCfg_cfgCwgph2HssL0TxDiv      ,
    CpuMacClockTreeCfg_cfgDivideHssL0TxDiv      ,
    CpuMacClockTreeCfg_cfgEdgeHssL0TxDiv        ,
    CpuMacClockTreeCfg_cfgExternalHssL0TxDiv    ,
    CpuMacClockTreeCfg_cfgHssL0Tx2RxLoopBackEn  ,
    CpuMacClockTreeCfg_cfgHssLane0And2SwapEn    ,
    CpuMacClockTreeCfg_cfgHssTxDataOutSelLane0  ,
    CpuMacClockTreeCfg_cfgInvertHssL0TxDiv      ,
    CpuMacClockTreeCfg_cfgLocalgoHssL0TxDiv     ,
    CpuMacClockTreeCfg_cfgResetHssL0TxDiv       ,
    CpuMacClockTreeCfg_cfgResetHssL0TxDiv2      ,
    CpuMacClockTreeCfg_cfgWidthHssL0TxDiv       ,
    CpuMacClockTreeCfg_TOTALCNT                 
}sys_at_cpumac_clocktree_cfg_item_t;

#define SYS_AT_PP_SUB_NETWORK_CHAN_NUM 24
#define SYS_AT_SUB_CHAN_IS_NETWORK(subChanId) ((subChanId & 0x1F) < SYS_AT_PP_SUB_NETWORK_CHAN_NUM)

#define SYS_AT_DMA_SUB_CHANNID0                ((0<<8) | (0<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID1                ((0<<8) | (1<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID2                ((0<<8) | (2<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID3                ((0<<8) | (3<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID4                ((1<<8) | (0<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID5                ((1<<8) | (1<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID6                ((1<<8) | (2<<6) | (0<<5) | 0x18)
#define SYS_AT_DMA_SUB_CHANNID7                ((1<<8) | (3<<6) | (0<<5) | 0x18)


#define SYS_AT_CPUMAC_SUB_CHANNID0              ((0<<8) | (0<<6) | (1<<5) | 0x18)
#define SYS_AT_CPUMAC_SUB_CHANNID1              ((0<<8) | (1<<6) | (1<<5) | 0x18)
#define SYS_AT_CPUMAC_SUB_CHANNID2              ((1<<8) | (0<<6) | (1<<5) | 0x18)
#define SYS_AT_CPUMAC_SUB_CHANNID3              ((1<<8) | (1<<6) | (1<<5) | 0x18)


#define SYS_AT_OAM_SUB_CHANNID(ppid, core_pp_num) ((((ppid)/(core_pp_num))<<8) | (((ppid) % (core_pp_num))<<6) | (1<<5) | 0x18)
#define SYS_AT_OAM_SUB_CHANNID1                 ((0<<8) | (3<<6) | (1<<5) | 0x18)
#define SYS_AT_OAM_SUB_CHANNID2                 ((1<<8) | (2<<6) | (1<<5) | 0x18)
#define SYS_AT_OAM_SUB_CHANNID3                 ((1<<8) | (3<<6) | (1<<5) | 0x18)

#define SYS_AT_LOOP_SUB_CHANNID0            ((0<<8) | (0<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID1            ((0<<8) | (0<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID2            ((0<<8) | (1<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID3            ((0<<8) | (1<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID4            ((0<<8) | (2<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID5            ((0<<8) | (2<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID6            ((0<<8) | (3<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID7            ((0<<8) | (3<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID8            ((1<<8) | (0<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID9            ((1<<8) | (0<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID10           ((1<<8) | (1<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID11           ((1<<8) | (1<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID12           ((1<<8) | (2<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID13           ((1<<8) | (2<<6) | (1<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID14           ((1<<8) | (3<<6) | (0<<5) | 0x19)
#define SYS_AT_LOOP_SUB_CHANNID15           ((1<<8) | (3<<6) | (1<<5) | 0x19)

struct sys_at_datapath_global_cfg_s
{
    uint16 port_num;  /* number of ports that is using */
    ctc_datapath_global_cfg_t* p_dp_cfg;
    uint8 mac_pcs_mode[AT_MCMAC_NUM_PER_CORE][AT_MAC_ID_NUM_PER_MCMAC];
};
typedef struct sys_at_datapath_global_cfg_s sys_at_datapath_global_cfg_t;

extern uint8 sys_at_datapath_get_chip_type(uint8 lchip);
extern uint8 sys_at_datapath_chip_is_dc(uint8 lchip);
extern uint8 sys_at_datapath_mac_group_is_valid(uint8 lchip, uint8 core_id, uint8 mac_group_id);
extern uint8 sys_at_datapath_pp_is_valid(uint8 lchip, uint8 core_id, uint8 pp_id);
extern uint8 _sys_at_datapath_serdes_scale(uint8 lchip);

#ifdef __cplusplus
}
#endif

#endif

